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Application Note 9707
TABLE 1. HI5805 EVALUATION BOARD POWER SUPPLIES
converter. The HI5805 clock input trigger level is approximately
POWER
SUPPLY
+5VAIN
+5VAIN1
-5VAIN
+5VDIN
NOMINAL
VALUE
5.0V ± 5%
5.0V ± 5%
-5.0V ± 5%
5.0V ± 5%3
CURRENT
(TYP)
22mA
46mA
22mA
43mA
FUNCTION(S)
SUPPLIED
Op Amps
A/D AV CC
Op Amps
CLK Comparator,
1.5V. Therefore, the duty cycle of the sampling clock should be
measured at this 1.5V trigger level. Test point TP4 provides a
convenient point to monitor the sample clock duty cycle and
make any required adjustments.
Figure 5 shows the sample clock and digital data timing
relationship for the evaluation board. The data
D0-D11 D-FF
corresponding to a particular sample will be available at the
+5VD1IN
5.0V ± 5%
13mA
A/D DV CC1 and
digital data outputs of the HI5805 after the data latency time,
DV CC2
t LAT , of 3 sample clock cycles plus the HI5805 digital data
+5VD2IN
-5VDIN
5.0V ± 5%
-5.0V ± 5%
1mA
3mA
A/D DV CC3
CLK Comparator
output delay, t OD . Table 2 lists the values that can be
expected for the indicated timing delays. Refer to the HI5805
data sheet for additional timing information.
It should be noted that overdriving the analog input beyond
the ± 2.0V fullscale input voltage range will not damage the
converter as long as the overdrive voltage stays within the
converters analog supply voltages. In the event of an
overdrive condition the converter will recover within one
sample clock cycle.
Sample Clock Driver, Timing and I/O
In order to ensure rated performance of the HI5805, the duty
cycle of the sample clock should be held at 50% ± 5%. It must
also have low phase noise and operate at standard TTL levels.
A voltage comparator (U3) with TTL output levels is provided on
the evaluation board to generate the sampling clock for the
HI5805 when a sinewave (< ± 3V) or squarewave clock is
The sample clock and digital output data signals are made
available through two connectors contained on the evaluation
board. The line buffering provided by the data output latches
allows for driving long leads or analyzer inputs. These data
latches are not necessary for the digital output data if the load
presented to the converter does not exceed the data sheet load
limits of one standard TTL load and 10pF. The P1 I/O connector
allows the evaluation board to be interfaced to the DSP
evaluation boards available from Intersil. Alternatively, the
digital output data and sample clock can also be accessed by
clipping the test leads of a logic analyzer or data acquisition
system onto the I/O pins of connector header P2.
TABLE 2. TIMING SPECIFICATIONS
applied to the CLK input (J1) of the evaluation board. A
potentiometer (VR1) is provided to allow the user to adjust the
duty cycle of the sampling clock to obtain the best performance
from the ADC and to allow the user to investigate the effects of
expected duty cycle variations on the performance of the
PARAMETER
t OD
t PD1
t PD2
DESCRIPTION
HI5805 Digital Output Data Delay
U3 Prop Delay
U5/6 Prop Delay
TYP
8ns
4.5ns
9ns
SINEWAVE CLK IN
(J1)
t PD1
HI5805 SAMPLE
CLOCK INPUT
(CLK)
t OD
HI5805 DIGITAL
DATA OUTPUT
DATA N-1
DATA N
(D0 - D11)
CLOCK OUT
(CLK AT TP4, P1-C20 OR P2-13)
t PD2
DIGITAL DATA OUTPUTS
(74ALS574)
DATA N-1
DATA N
FIGURE 5. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS
3-5
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